Power Device Lab

Simulated I-V, double-pulse switching, and Baliga-referenced analytical loss estimates
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Family
Class
Material
Diamond: 3 local VD refs vs Si 129. Missing critical VD setup: mobility defaults, SRH/Auger lifetimes, A.EDB/A.EAB dopant levels, and a calibrated impact-ionization model.

User-Defined Device Analysis

Punch-Through Drift Tuning

This view frames the fixed-width tradeoff: lock the drift thickness, sweep drift doping, and compare the punch-through and avalanche limits at constant geometry.

At fixed Wfix, higher ND lowers Rdrift,sp, raises VPT, and lowers the avalanche limit, so the usable blocking point becomes BVeff = min(BVPT, BVAVL).
Wdep(V) = sqrt(2εsV/(qND)) BVPT ≈ qNDWfix2/(2εs) when Wdep = Wfix BVAVL ≈ εsEC2/(2qND) and BVeff ≈ min(BVPT, BVAVL) Rdrift,sp ≈ Wfix/(qμnND) so the knob mainly trades resistance against blocking margin ND* ≈ εsEC/(qWfix) marks the fixed-width crossover between punch-through-limited and avalanche-limited behavior
Nd,max
Wd,min
Rdrift,sp
I
Vdrop
Pcond
Uses the selected family above, then compares only against simulated devices in that family.
Material Class Design BV Ron,sp V @ J Pcond IRM Qrr trr Esw Psw
Drift: Baliga Eq. 1.9, 1.10, 1.11; resistance form Eq. 3.25. Critical field: Baliga Eq. 3.22 for Si and Eq. 3.23 for 4H-SiC. GaN uses the same project scaling form and is labeled as an extension. Loss: MOSFET on-state term follows Baliga Eq. 6.242; switching rows use Psw = Eswfsw.

Steady I-V

Forward Conduction
Reverse Blocking
Start values appear here.

Reverse Recovery + Switching Loss

Analytical Formula Sources

WD = 2BV/EC — Baliga Eq. 1.9. ND = εSEC²/(2qBV) — Baliga Eq. 1.10. Ron,sp = 4BV²/(εSµnEC³) — Baliga Eq. 1.11, repeated as Eq. 3.24. Ron,sp = WPP/(qµnND) — Baliga Eq. 3.25. EC(ND) scaling — Baliga Eq. 3.22 for Si and Eq. 3.23 for 4H-SiC. MOSFET PON = (tON/T)RONION² — Baliga Eq. 6.242.

Decks

steady.in + switching.in
Material Class Status Steady Switch